Preface xxvii

Acknowledgments xxxiii

PART I BASIC DIGITAL CIRCUITS DEVELOPMENT

1 Gate-Level Combinational Circuit 1

1.1 Introduction 1

1.1.1 Brief history of Verilog and SystemVerilog 1

1.1.2 Book coverage 2

1.2 General description 3

1.3 Basic lexical elements and data types 4

1.3.1 Lexical elements 4

1.3.2 Data types used in the book 5

1.3.3 Number representation 6

1.3.4 Operators 7

1.4 Program skeleton 7

1.4.1 Port declaration 7

1.4.2 Signal declaration 8

1.4.3 Program body 8

1.4.4 Concurrent semantics 9

1.4.5 Another example 10

1.5 Structural description 10

1.6 Top-level signal mapping 13

1.7 Testbench 14

1.8 Bibliographic notes 16

1.9 Suggested experiments 16

1.9.1 Code for gate-level greater-than circuit 17

1.9.2 Code for gate-level binary decoder 17

2 Overview of FPGA and EDA Software 19

2.1 FPGA 19

2.1.1 Overview of a general FPGA device 19

2.1.2 Overview of the Xilinx Artix-7 devices 20

2.2 Overview of the Digilent Nexys 4 DDR board 21

2.3 Development flow 22

2.4 Xilinx Vivado Design Suite 24

2.5 Bibliographic notes 24

2.6 Suggested experiments 24

2.6.1 Gate-level greater-than circuit 24

2.6.2 Gate-level binary decoder 26

3 RT-Level Combinational Circuit 29

3.1 Operators 29

3.1.1 Arithmetic operators 31

3.1.2 Shift operators 31

3.1.3 Relational and equality operators 32

3.1.4 Bitwise, reduction, and logical operators 32

3.1.5 Concatenation and replication operators 33

3.1.6 Conditional operators 34

3.1.7 Operator precedence 35

3.1.8 Expression bit-length adjustment 35

3.1.9 Synthesis of z and x values 36

3.2 Always block for a combinational circuit 38

3.2.1 Overview of always block 39

3.2.2 Procedural assignment 40

3.2.3 Conceptual examples 40

3.3 Coding guidelines 43

3.4 If statement 43

3.4.1 Syntax 43

3.4.2 Examples 44

3.5 Case statement 45

3.5.1 Syntax 45

3.5.2 Examples 46

3.5.3 The casez and casex statements 47

3.5.4 Full case and parallel case 48

3.6 Routing structure of conditional control constructs 49

3.6.1 Priority routing network 49

3.6.2 Multiplexing network 51

3.7 Additional coding guidelines for an always block 52

3.7.1 Common errors in combinational circuit codes 52

3.7.2 Guidelines 56

3.8 Parameter and constant 56

3.8.1 Constant 56

3.8.2 Parameter 58

3.9 Replicated structure 59

3.9.1 Generate-for statement 59

3.9.2 Procedural-for statement 60

3.9.3 Example 60

3.10 Design examples 62

3.10.1 Hexadecimal digit to seven-segment LED decoder 62

3.10.2 Sign-magnitude adder 65

3.10.3 Barrel shifter 68

3.10.4 Simplified floating-point adder 69

3.11 Bibliographic notes 73

3.12 Suggested experiments 73

3.12.1 Multi-function barrel shifter 73

3.12.2 Parameterized barrel shifter 74

3.12.3 Dual-priority encoder 74

3.12.4 BCD incrementor 74

3.12.5 Floating-point greater-than circuit 74

3.12.6 Floating-point and signed integer conversion circuit 74

3.12.7 Enhanced floating-point adder 75

4 Regular Sequential Circuit 77

4.1 Introduction 77

4.1.1 D FF and register 78

4.1.2 Basic block system 78

4.1.3 Code development 79

4.1.4 Sequential circuit coding guidelines and style 79

4.2 HDL code of the FF and register 80

4.2.1 D FF 80

4.2.2 Register 85

4.3 Simple design examples 85

4.3.1 Shift register 85

4.3.2 Binary counter and variant 87

4.4 Testbench for sequential circuits 89

4.5 Case study 93

4.5.1 LED time-multiplexing circuit 93

4.5.2 Stopwatch 101

4.6 Timing and clocking 104

4.6.1 Timing of FF 104

4.6.2 Maximum operating frequency 104

4.6.3 Clock tree 107

4.6.4 GALS system and CDC 107

4.7 Bibliographic notes 108

4.8 Suggested experiments 108

4.8.1 Programmable square wave generator 108

4.8.2 PWM and LED dimmer 108

4.8.3 Rotating square circuit 109

4.8.4 Heartbeat circuit 109

4.8.5 Rotating LED banner circuit 109

4.8.6 Enhanced stopwatch 110

5 FSM 111

5.1 Introduction 111

5.1.1 Mealy and Moore outputs 112

5.1.2 FSM representation 112

5.2 FSM code development 115

5.2.1 Enumerated data type and state assignment 115

5.2.2 Multi-segment code 116

5.2.3 Two-segment code 117

5.3 Design examples 118

5.3.1 Rising-edge detector 118

5.3.2 Debouncing circuit 123

5.3.3 Testing circuit 126

5.4 Bibliographic notes 128

5.5 Suggested experiments 128

5.5.1 Dual-edge detector 128

5.5.2 Early detection debouncing circuit 128

5.5.3 Parking lot occupancy counter 129

6 FSMD 131

6.1 Introduction 131

6.1.1 Single RT operation 132

6.1.2 ASMD chart 132

6.1.3 Decision box with a register 134

6.2 Code development of an FSMD 137

6.2.1 Debouncing circuit based on RT methodology 137

6.2.2 Code with explicit data path components 137

6.2.3 Code with implicit data path components 140

6.2.4 Comparison 142

6.3 Design examples 144

6.3.1 Fibonacci number circuit 144

6.3.2 Division circuit 147

6.3.3 Binary-to-BCD conversion circuit 150

6.3.4 Period counter 153

6.3.5 Accurate low-frequency counter 156

6.4 Bibliographic notes 159

6.5 Suggested experiments 159

6.5.1 Early detection debouncing circuit 159

6.5.2 BCD-to-binary conversion circuit 160

6.5.3 Fibonacci circuit with BCD I/O: design approach 1 160

6.5.4 Fibonacci circuit with BCD I/O: design approach 2 160

6.5.5 Auto-scaled low-frequency counter 161

6.5.6 Reaction timer 161

6.5.7 Babbage difference engine emulation circuit 162

7 RAM and Buffer of FPGA 165

7.1 Embedded memory of FPGA device 165

7.1.1 Memory of an Artix device 166

7.1.2 Memory available in the Nexys 4 DDR board 166

7.2 General description for a RAM-like component 167

7.2.1 Register file 167

7.2.2 Dynamic array indexing operation 169

7.2.3 Key aspects of a RAM module 170

7.2.4 Genuine ROM 171

7.3 FIFO buffer 173

7.3.1 FIFO read configuration 174

7.3.2 Circular queue implementation 175

7.4 HDL templates for memory inference 178

7.4.1 Methods to incorporate memory modules 178

7.4.2 Synchronous dual-port RAM 179

7.4.3 "Simple" synchronous dual-port RAM 180

7.4.4 Synchronous single-port RAM 181

7.4.5 Synchronous ROM 182

7.4.6 BRAM-based FIFO buffer 183

7.4.7 Design considerations 183

7.5 Overview of memory controller 184

7.6 Bibliographic notes 185

7.7 Suggested experiments 186

7.7.1 ROM-based sign-magnitude adder 186

7.7.2 ROM-based temperature conversion 186

7.7.3 FIFO with data width conversion 186

7.7.4 Standard FIFO to FWFT FIFO conversion circuit 187

7.7.5 FIFO buffer with extended status 187

7.7.6 Stack 187

8 Selected Topics of SystemVerilog 189

8.1 Timing model 189

8.1.1 Concurrent constructs 190

8.1.2 Assignment statement 190

8.1.3 Basic model 190

8.1.4 Blocking versus nonblocking assignment 192

8.2 Coding guidelines revisited 194

8.2.1 "Single variable assignment" guideline 195

8.2.2 "Blocking assignment for combinational circuit" guideline 195

8.2.3 "Nonblocking assignment for register" guideline 197

8.3 Alternative coding style 198

8.3.1 First coding style revisited 198

8.3.2 Sequential circuit with mixed blocking and nonblocking assignments 199

8.3.3 Combined coding style 201

8.3.4 Summary 206

8.4 Data types 206

8.4.1 The net and variable types 206

8.4.2 The logic data type 207

8.4.3 Limitation of the logic data type 208

8.4.4 New data types in SystemVerilog 208

8.5 Use of the signed data type 209

8.5.1 Overview 209

8.5.2 Signed number conversion 210

8.6 Bibliographic notes 211

8.7 Suggested experiments 211

8.7.1 Shift register with blocking and nonblocking assignments 211

8.7.2 Alternative coding style for the BCD counter 212

8.7.3 Alternative coding style for the FIFO buffer 212

8.7.4 Alternative coding style for the Fibonacci circuit 212

8.7.5 Dual-mode comparator 212

PART II EMBEDDED SOC I: VANILLA FPRO SYSTEM

9 Overview of Embedded SoC Systems 215

9.1 Embedded SoC 215

9.1.1 Overview of embedded systems 215

9.1.2 FPGA-based SoC 216

9.1.3 IP cores 216

9.2 Development flow of the embedded SoC 217

9.2.1 Hardware-software partition 217

9.2.2 Hardware development flow 217

9.2.3 Software development flow 219

9.2.4 Physical implementation and test 219

9.2.5 Custom IP core development 219

9.3 FPro SoC Platform 220

9.3.1 Motivations 220

9.3.2 Platform hardware organization 221

9.3.3 Platform software organization 223

9.3.4 Modified development flow 224

9.4 Adaptation on the Digilent Nexys 4 DDR board 224

9.5 Portability 226

9.5.1 Processor Module and Bridge 226

9.5.2 MMIO subsystem 227

9.5.3 Video subsystem 227

9.6 Organization 228

9.7 Bibliographic notes 228

10 Bare Metal System Software Development 231

10.1 Bare metal system development overview...