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Wafer-Level Chip-Scale Packaging
Analog and Power Semiconductor Applications
Taschenbuch von Yong Liu (u. a.)
Sprache: Englisch

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Beschreibung
Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. Along with new analog and power WLCSP development, the roleof modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical and stress modeling methodologies is also presented in the book.
Analog and Power Wafer Level Chip Scale Packaging presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Since the analog and power electronic wafer level packaging is different from regular digital and memory IC package, this book will systematically introduce the typical analog and power electronic wafer level packaging design, assembly process, materials, reliability and failure analysis, and material selection. Along with new analog and power WLCSP development, the roleof modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical and stress modeling methodologies is also presented in the book.
Zusammenfassung

Covers the development of wafer level power discrete packaging with regular wafer level design concept and directly bumping technology

Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology

Presents the wafer level analog IC packaging design through fan-in and fan-out with RDLs

Inhaltsverzeichnis

Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging.- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package.- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package.- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design.- Chapter 5. Wafer Level Discrete Power MOSFET Package Design.- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution.- Chapter 7. Thermal Management, Design, Analysis for WLCSP.- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP.- Chapter 9. WLCSP Typical Assembly Process.- Chapter 10. WLCSP Typical Reliability and Test.

Details
Erscheinungsjahr: 2016
Fachbereich: Nachrichtentechnik
Genre: Importe, Technik
Rubrik: Naturwissenschaften & Technik
Medium: Taschenbuch
Inhalt: xvii
322 S.
58 s/w Illustr.
256 farbige Illustr.
322 p. 314 illus.
256 illus. in color.
ISBN-13: 9781493954384
ISBN-10: 1493954385
Sprache: Englisch
Einband: Kartoniert / Broschiert
Autor: Liu, Yong
Qu, Shichun
Auflage: Softcover reprint of the original 1st edition 2015
Hersteller: Springer US
Springer New York
Springer US, New York, N.Y.
Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, D-69121 Heidelberg, juergen.hartmann@springer.com
Maße: 235 x 155 x 18 mm
Von/Mit: Yong Liu (u. a.)
Erscheinungsdatum: 23.08.2016
Gewicht: 0,578 kg
Artikel-ID: 107556559
Zusammenfassung

Covers the development of wafer level power discrete packaging with regular wafer level design concept and directly bumping technology

Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology

Presents the wafer level analog IC packaging design through fan-in and fan-out with RDLs

Inhaltsverzeichnis

Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging.- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package.- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package.- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design.- Chapter 5. Wafer Level Discrete Power MOSFET Package Design.- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution.- Chapter 7. Thermal Management, Design, Analysis for WLCSP.- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP.- Chapter 9. WLCSP Typical Assembly Process.- Chapter 10. WLCSP Typical Reliability and Test.

Details
Erscheinungsjahr: 2016
Fachbereich: Nachrichtentechnik
Genre: Importe, Technik
Rubrik: Naturwissenschaften & Technik
Medium: Taschenbuch
Inhalt: xvii
322 S.
58 s/w Illustr.
256 farbige Illustr.
322 p. 314 illus.
256 illus. in color.
ISBN-13: 9781493954384
ISBN-10: 1493954385
Sprache: Englisch
Einband: Kartoniert / Broschiert
Autor: Liu, Yong
Qu, Shichun
Auflage: Softcover reprint of the original 1st edition 2015
Hersteller: Springer US
Springer New York
Springer US, New York, N.Y.
Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, D-69121 Heidelberg, juergen.hartmann@springer.com
Maße: 235 x 155 x 18 mm
Von/Mit: Yong Liu (u. a.)
Erscheinungsdatum: 23.08.2016
Gewicht: 0,578 kg
Artikel-ID: 107556559
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